Processor |
AVX2 Ratio Offset |
0.0x
(0.0 - 31.0x)
|
AVX2 Voltage Guardband Scale Factor |
1.000x
(0.000 - 2.000x)
|
Core Voltage |
DefaultV
(Default - UndefinedV)
|
Core Voltage Offset |
0.0000mV
(-1.0000 - UndefinedmV)
|
Efficient Core Ratio |
36x
(36 - 50x)
|
Performance Core Ratio |
47x
(36 - 50x)
|
Processor Core IccMax |
280.000A
(1.000 - 4294967294.000A)
|
Reference Clock |
DefaultMHz
(Default - 200.000MHz)
|
Core Voltage Mode |
Adaptive
|
Intel® Overclocking Thermal Velocity Boost |
Disable
|
Processor.Turbo.VoltageOverride |
Performance Core 0 Voltage Override |
DefaultV
(Default - 2.000V)
|
Performance Core 1 Voltage Override |
DefaultV
(Default - 2.000V)
|
Performance Core 2 Voltage Override |
DefaultV
(Default - 2.000V)
|
Performance Core 3 Voltage Override |
DefaultV
(Default - 2.000V)
|
Performance Core 4 Voltage Override |
DefaultV
(Default - 2.000V)
|
Performance Core 5 Voltage Override |
DefaultV
(Default - 2.000V)
|
Performance Core 6 Voltage Override |
DefaultV
(Default - 2.000V)
|
Performance Core 7 Voltage Override |
DefaultV
(Default - 2.000V)
|
Processor.Turbo.VoltageOffset |
Performance Core 0 Voltage Offset |
0.000mV
(-1.000 - 0.999mV)
|
Performance Core 1 Voltage Offset |
0.000mV
(-1.000 - 0.999mV)
|
Performance Core 2 Voltage Offset |
0.000mV
(-1.000 - 0.999mV)
|
Performance Core 3 Voltage Offset |
0.000mV
(-1.000 - 0.999mV)
|
Performance Core 4 Voltage Offset |
0.000mV
(-1.000 - 0.999mV)
|
Performance Core 5 Voltage Offset |
0.000mV
(-1.000 - 0.999mV)
|
Performance Core 6 Voltage Offset |
0.000mV
(-1.000 - 0.999mV)
|
Performance Core 7 Voltage Offset |
0.000mV
(-1.000 - 0.999mV)
|
Processor.Turbo.VoltageMode |
Performance Core 0 Voltage Mode |
Adaptive
|
Performance Core 1 Voltage Mode |
Adaptive
|
Performance Core 2 Voltage Mode |
Adaptive
|
Performance Core 3 Voltage Mode |
Adaptive
|
Performance Core 4 Voltage Mode |
Adaptive
|
Performance Core 5 Voltage Mode |
Adaptive
|
Performance Core 6 Voltage Mode |
Adaptive
|
Performance Core 7 Voltage Mode |
Adaptive
|
Processor.Turbo.TVBTemperature2 |
Temperature Cutoff (#2) for 1 Active P-Core |
0°C
(4294967293 - 100°C)
|
Temperature Cutoff (#2) for 2 Active P-Cores |
0°C
(4294967293 - 100°C)
|
Temperature Cutoff (#2) for 3 Active P-Cores |
0°C
(4294967293 - 100°C)
|
Temperature Cutoff (#2) for 4 Active P-Cores |
0°C
(4294967293 - 100°C)
|
Temperature Cutoff (#2) for 5 Active P-Cores |
0°C
(4294967293 - 100°C)
|
Temperature Cutoff (#2) for 6 Active P-Cores |
0°C
(4294967293 - 100°C)
|
Temperature Cutoff (#2) for 7 Active P-Cores |
0°C
(4294967293 - 100°C)
|
Temperature Cutoff (#2) for 8 Active P-Cores |
0°C
(4294967293 - 100°C)
|
Processor.Turbo.TVBTemperature |
Temperature Cutoff for 1 Active P-Core |
0°C
(4294967293 - 100°C)
|
Temperature Cutoff for 2 Active P-Cores |
0°C
(4294967293 - 100°C)
|
Temperature Cutoff for 3 Active P-Cores |
0°C
(4294967293 - 100°C)
|
Temperature Cutoff for 4 Active P-Cores |
0°C
(4294967293 - 100°C)
|
Temperature Cutoff for 5 Active P-Cores |
0°C
(4294967293 - 100°C)
|
Temperature Cutoff for 6 Active P-Cores |
0°C
(4294967293 - 100°C)
|
Temperature Cutoff for 7 Active P-Cores |
0°C
(4294967293 - 100°C)
|
Temperature Cutoff for 8 Active P-Cores |
0°C
(4294967293 - 100°C)
|
Processor.Turbo.TVBRatioOffset2 |
Ratio Offset (#2) for 1 Active P-Core |
4294967293x
(4294967293 - 20x)
|
Ratio Offset (#2) for 2 Active P-Cores |
4294967293x
(4294967293 - 20x)
|
Ratio Offset (#2) for 3 Active P-Cores |
4294967293x
(4294967293 - 20x)
|
Ratio Offset (#2) for 4 Active P-Cores |
4294967293x
(4294967293 - 20x)
|
Ratio Offset (#2) for 5 Active P-Cores |
4294967293x
(4294967293 - 20x)
|
Ratio Offset (#2) for 6 Active P-Cores |
4294967293x
(4294967293 - 20x)
|
Ratio Offset (#2) for 7 Active P-Cores |
4294967293x
(4294967293 - 20x)
|
Ratio Offset (#2) for 8 Active P-Cores |
4294967293x
(4294967293 - 20x)
|
Processor.Turbo.TVBRatioOffset |
Ratio Offset for 1 Active P-Core |
4294967293x
(4294967293 - 20x)
|
Ratio Offset for 2 Active P-Cores |
4294967293x
(4294967293 - 20x)
|
Ratio Offset for 3 Active P-Cores |
4294967293x
(4294967293 - 20x)
|
Ratio Offset for 4 Active P-Cores |
4294967293x
(4294967293 - 20x)
|
Ratio Offset for 5 Active P-Cores |
4294967293x
(4294967293 - 20x)
|
Ratio Offset for 6 Active P-Cores |
4294967293x
(4294967293 - 20x)
|
Ratio Offset for 7 Active P-Cores |
4294967293x
(4294967293 - 20x)
|
Ratio Offset for 8 Active P-Cores |
4294967293x
(4294967293 - 20x)
|
Processor.Turbo.Ratios |
1 Active Performance Core |
50x
(36 - 50x)
|
2 Active Performance Cores |
49x
(36 - 50x)
|
3 Active Performance Cores |
49x
(36 - 50x)
|
4 Active Performance Cores |
49x
(36 - 50x)
|
5 Active Performance Cores |
48x
(36 - 50x)
|
6 Active Performance Cores |
48x
(36 - 50x)
|
7 Active Performance Cores |
47x
(36 - 50x)
|
8 Active Performance Cores |
47x
(36 - 50x)
|
Processor.Turbo.RatioLimit |
Performance Core 0 |
49x
(36 - 50x)
|
Performance Core 1 |
49x
(36 - 50x)
|
Performance Core 2 |
49x
(36 - 50x)
|
Performance Core 3 |
49x
(36 - 50x)
|
Performance Core 4 ★ |
50x
(36 - 50x)
|
Performance Core 5 |
49x
(36 - 50x)
|
Performance Core 6 ★ |
50x
(36 - 50x)
|
Performance Core 7 |
49x
(36 - 50x)
|
Processor.Turbo.ProcessorCoreTVBTemperature2 |
Performance Core 0 Temperature Cutoff (#2) |
0°C
(4294967293 - 100°C)
|
Performance Core 1 Temperature Cutoff (#2) |
0°C
(4294967293 - 100°C)
|
Performance Core 2 Temperature Cutoff (#2) |
0°C
(4294967293 - 100°C)
|
Performance Core 3 Temperature Cutoff (#2) |
0°C
(4294967293 - 100°C)
|
Performance Core 4 Temperature Cutoff (#2) |
0°C
(4294967293 - 100°C)
|
Performance Core 5 Temperature Cutoff (#2) |
0°C
(4294967293 - 100°C)
|
Performance Core 6 Temperature Cutoff (#2) |
0°C
(4294967293 - 100°C)
|
Performance Core 7 Temperature Cutoff (#2) |
0°C
(4294967293 - 100°C)
|
Processor.Turbo.ProcessorCoreTVBTemperature |
Performance Core 0 Temperature Cutoff |
0°C
(4294967293 - 100°C)
|
Performance Core 1 Temperature Cutoff |
0°C
(4294967293 - 100°C)
|
Performance Core 2 Temperature Cutoff |
0°C
(4294967293 - 100°C)
|
Performance Core 3 Temperature Cutoff |
0°C
(4294967293 - 100°C)
|
Performance Core 4 Temperature Cutoff |
0°C
(4294967293 - 100°C)
|
Performance Core 5 Temperature Cutoff |
0°C
(4294967293 - 100°C)
|
Performance Core 6 Temperature Cutoff |
0°C
(4294967293 - 100°C)
|
Performance Core 7 Temperature Cutoff |
0°C
(4294967293 - 100°C)
|
Processor.Turbo.ProcessorCoreTVBRatioOffset2 |
Performance Core 0 Ratio Offset (#2) |
4294967293x
(4294967293 - 20x)
|
Performance Core 1 Ratio Offset (#2) |
4294967293x
(4294967293 - 20x)
|
Performance Core 2 Ratio Offset (#2) |
4294967293x
(4294967293 - 20x)
|
Performance Core 3 Ratio Offset (#2) |
4294967293x
(4294967293 - 20x)
|
Performance Core 4 Ratio Offset (#2) |
4294967293x
(4294967293 - 20x)
|
Performance Core 5 Ratio Offset (#2) |
4294967293x
(4294967293 - 20x)
|
Performance Core 6 Ratio Offset (#2) |
4294967293x
(4294967293 - 20x)
|
Performance Core 7 Ratio Offset (#2) |
4294967293x
(4294967293 - 20x)
|
Processor.Turbo.ProcessorCoreTVBRatioOffset |
Performance Core 0 Ratio Offset |
4294967293x
(4294967293 - 20x)
|
Performance Core 1 Ratio Offset |
4294967293x
(4294967293 - 20x)
|
Performance Core 2 Ratio Offset |
4294967293x
(4294967293 - 20x)
|
Performance Core 3 Ratio Offset |
4294967293x
(4294967293 - 20x)
|
Performance Core 4 Ratio Offset |
4294967293x
(4294967293 - 20x)
|
Performance Core 5 Ratio Offset |
4294967293x
(4294967293 - 20x)
|
Performance Core 6 Ratio Offset |
4294967293x
(4294967293 - 20x)
|
Performance Core 7 Ratio Offset |
4294967293x
(4294967293 - 20x)
|
Processor.Turbo.EfficientCoreVoltageOverride |
Efficient Core 0 Voltage Override |
DefaultV
(Default - 2.000V)
|
Efficient Core 1 Voltage Override |
DefaultV
(Default - 2.000V)
|
Efficient Core 2 Voltage Override |
DefaultV
(Default - 2.000V)
|
Efficient Core 3 Voltage Override |
DefaultV
(Default - 2.000V)
|
Processor.Turbo.EfficientCoreVoltageOffset |
Efficient Core 0 Voltage Offset |
0.000mV
(-1.000 - 0.999mV)
|
Efficient Core 1 Voltage Offset |
0.000mV
(-1.000 - 0.999mV)
|
Efficient Core 2 Voltage Offset |
0.000mV
(-1.000 - 0.999mV)
|
Efficient Core 3 Voltage Offset |
0.000mV
(-1.000 - 0.999mV)
|
Processor.Turbo.EfficientCoreVoltageMode |
Efficient Core 0 Voltage Mode |
Adaptive
|
Efficient Core 1 Voltage Mode |
Adaptive
|
Efficient Core 2 Voltage Mode |
Adaptive
|
Efficient Core 3 Voltage Mode |
Adaptive
|
Processor.Turbo.EfficientCoreRatios |
1 Active Efficient Core |
38x
(36 - 50x)
|
2 Active Efficient Cores |
38x
(36 - 50x)
|
3 Active Efficient Cores |
36x
(36 - 50x)
|
4 Active Efficient Cores |
36x
(36 - 50x)
|
Processor.Turbo.EfficientCoreRatioLimit |
Efficient Core 0 |
38x
(36 - 50x)
|
Efficient Core 1 |
38x
(36 - 50x)
|
Efficient Core 2 |
38x
(36 - 50x)
|
Efficient Core 3 |
38x
(36 - 50x)
|
Processor.Turbo |
Processor.PowerCurrent |
Turbo Boost Power Max |
125.000W
(1.000 - 4095.875W)
|
Turbo Boost Power Time Window |
56Seconds
(1 - 128Seconds)
|
Turbo Boost Short Power Max |
265.000W
(1.000 - 4095.875W)
|
Package Turbo Power Lock |
Disable
|
Turbo Boost Short Power Max Enable |
Enable
|
Other |
System Agent Voltage |
DefaultV
(Default - 2.000V)
|
System Agent Voltage Offset |
0mV
(-1 - 1mV)
|
System Agent Voltage Mode |
Adaptive
|
Memory.XMP |
CommandRate |
0n
(0 - 3n)
|
CommandRate |
0n
(0 - 3n)
|
CommandRate |
0n
(0 - 3n)
|
CommandRate |
0n
(0 - 3n)
|
CommandRate |
0n
(0 - 3n)
|
CommandRate |
0n
(0 - 3n)
|
CommandRate |
0n
(0 - 3n)
|
CommandRate |
0n
(0 - 3n)
|
CommandRate |
0n
(0 - 3n)
|
CommandRate |
0n
(0 - 3n)
|
CommandRate |
0n
(0 - 3n)
|
CommandRate |
0n
(0 - 3n)
|
CommandRate |
0n
(0 - 3n)
|
CommandRate |
0n
(0 - 3n)
|
CommandRate |
0n
(0 - 3n)
|
CommandRate |
0n
(0 - 3n)
|
Frequency |
0MHz
(0 - 2403MHz)
|
Frequency |
2403MHz
(990 - 2403MHz)
|
Frequency |
0MHz
(0 - 2403MHz)
|
Frequency |
2604MHz
(990 - 2604MHz)
|
Frequency |
0MHz
(0 - 2403MHz)
|
Frequency |
2403MHz
(990 - 2403MHz)
|
Frequency |
0MHz
(0 - 2403MHz)
|
Frequency |
2403MHz
(990 - 2403MHz)
|
Frequency |
0MHz
(0 - 2403MHz)
|
Frequency |
2604MHz
(990 - 2604MHz)
|
Frequency |
2403MHz
(990 - 2403MHz)
|
Frequency |
0MHz
(0 - 2403MHz)
|
Frequency |
2604MHz
(990 - 2604MHz)
|
Frequency |
0MHz
(0 - 2403MHz)
|
Frequency |
0MHz
(0 - 2403MHz)
|
Frequency |
2604MHz
(990 - 2604MHz)
|
MCVoltage |
UndefinedV
(0.50 - UndefinedV)
|
MCVoltage |
UndefinedV
(0.50 - UndefinedV)
|
MCVoltage |
0.00V
(0.00 - UndefinedV)
|
MCVoltage |
0.00V
(0.00 - UndefinedV)
|
MCVoltage |
UndefinedV
(0.50 - UndefinedV)
|
MCVoltage |
0.00V
(0.00 - UndefinedV)
|
MCVoltage |
UndefinedV
(0.50 - UndefinedV)
|
MCVoltage |
UndefinedV
(0.50 - UndefinedV)
|
MCVoltage |
0.00V
(0.00 - UndefinedV)
|
MCVoltage |
0.00V
(0.00 - UndefinedV)
|
MCVoltage |
0.00V
(0.00 - UndefinedV)
|
MCVoltage |
0.00V
(0.00 - UndefinedV)
|
MCVoltage |
UndefinedV
(0.50 - UndefinedV)
|
MCVoltage |
UndefinedV
(0.50 - UndefinedV)
|
MCVoltage |
UndefinedV
(0.50 - UndefinedV)
|
MCVoltage |
0.00V
(0.00 - UndefinedV)
|
VDD |
1.10V
(0.80 - UndefinedV)
|
VDD |
0.00V
(0.00 - UndefinedV)
|
VDD |
1.25V
(0.80 - UndefinedV)
|
VDD |
1.25V
(0.80 - UndefinedV)
|
VDD |
1.25V
(0.80 - UndefinedV)
|
VDD |
1.10V
(0.80 - UndefinedV)
|
VDD |
0.00V
(0.00 - UndefinedV)
|
VDD |
0.00V
(0.00 - UndefinedV)
|
VDD |
0.00V
(0.00 - UndefinedV)
|
VDD |
0.00V
(0.00 - UndefinedV)
|
VDD |
1.10V
(0.80 - UndefinedV)
|
VDD |
0.00V
(0.00 - UndefinedV)
|
VDD |
0.00V
(0.00 - UndefinedV)
|
VDD |
1.10V
(0.80 - UndefinedV)
|
VDD |
0.00V
(0.00 - UndefinedV)
|
VDD |
1.25V
(0.80 - UndefinedV)
|
VDDQ |
0.00V
(0.00 - UndefinedV)
|
VDDQ |
1.25V
(0.80 - UndefinedV)
|
VDDQ |
0.00V
(0.00 - UndefinedV)
|
VDDQ |
1.10V
(0.80 - UndefinedV)
|
VDDQ |
1.10V
(0.80 - UndefinedV)
|
VDDQ |
0.00V
(0.00 - UndefinedV)
|
VDDQ |
0.00V
(0.00 - UndefinedV)
|
VDDQ |
1.25V
(0.80 - UndefinedV)
|
VDDQ |
1.25V
(0.80 - UndefinedV)
|
VDDQ |
1.10V
(0.80 - UndefinedV)
|
VDDQ |
1.25V
(0.80 - UndefinedV)
|
VDDQ |
0.00V
(0.00 - UndefinedV)
|
VDDQ |
0.00V
(0.00 - UndefinedV)
|
VDDQ |
0.00V
(0.00 - UndefinedV)
|
VDDQ |
1.10V
(0.80 - UndefinedV)
|
VDDQ |
0.00V
(0.00 - UndefinedV)
|
VPP |
0.00V
(0.00 - UndefinedV)
|
VPP |
0.00V
(0.00 - UndefinedV)
|
VPP |
1.80V
(1.50 - UndefinedV)
|
VPP |
1.80V
(1.50 - UndefinedV)
|
VPP |
1.80V
(1.50 - UndefinedV)
|
VPP |
0.00V
(0.00 - UndefinedV)
|
VPP |
1.80V
(1.50 - UndefinedV)
|
VPP |
0.00V
(0.00 - UndefinedV)
|
VPP |
0.00V
(0.00 - UndefinedV)
|
VPP |
0.00V
(0.00 - UndefinedV)
|
VPP |
1.80V
(1.50 - UndefinedV)
|
VPP |
0.00V
(0.00 - UndefinedV)
|
VPP |
1.80V
(1.50 - UndefinedV)
|
VPP |
1.80V
(1.50 - UndefinedV)
|
VPP |
0.00V
(0.00 - UndefinedV)
|
VPP |
1.80V
(1.50 - UndefinedV)
|
tCCD_L |
0Cycles
(0 - 54Cycles)
|
tCCD_L |
0Cycles
(0 - 54Cycles)
|
tCCD_L |
0Cycles
(0 - 54Cycles)
|
tCCD_L |
0Cycles
(0 - 54Cycles)
|
tCCD_L |
0Cycles
(0 - 54Cycles)
|
tCCD_L |
0Cycles
(0 - 54Cycles)
|
tCCD_L |
0Cycles
(0 - 54Cycles)
|
tCCD_L |
0Cycles
(0 - 54Cycles)
|
tCCD_L |
0Cycles
(0 - 54Cycles)
|
tCCD_L |
0Cycles
(0 - 54Cycles)
|
tCCD_L |
0Cycles
(0 - 54Cycles)
|
tCCD_L |
0Cycles
(0 - 54Cycles)
|
tCCD_L |
0Cycles
(0 - 54Cycles)
|
tCCD_L |
0Cycles
(0 - 54Cycles)
|
tCCD_L |
0Cycles
(0 - 54Cycles)
|
tCCD_L |
0Cycles
(0 - 54Cycles)
|
tCCD_L_WR |
0Cycles
(0 - 54Cycles)
|
tCCD_L_WR |
0Cycles
(0 - 54Cycles)
|
tCCD_L_WR |
0Cycles
(0 - 54Cycles)
|
tCCD_L_WR |
0Cycles
(0 - 54Cycles)
|
tCCD_L_WR |
0Cycles
(0 - 54Cycles)
|
tCCD_L_WR |
0Cycles
(0 - 54Cycles)
|
tCCD_L_WR |
0Cycles
(0 - 54Cycles)
|
tCCD_L_WR |
0Cycles
(0 - 54Cycles)
|
tCCD_L_WR |
0Cycles
(0 - 54Cycles)
|
tCCD_L_WR |
0Cycles
(0 - 54Cycles)
|
tCCD_L_WR |
0Cycles
(0 - 54Cycles)
|
tCCD_L_WR |
0Cycles
(0 - 54Cycles)
|
tCCD_L_WR |
0Cycles
(0 - 54Cycles)
|
tCCD_L_WR |
0Cycles
(0 - 54Cycles)
|
tCCD_L_WR |
0Cycles
(0 - 54Cycles)
|
tCCD_L_WR |
0Cycles
(0 - 54Cycles)
|
tCCD_L_WR2 |
0Cycles
(0 - 145Cycles)
|
tCCD_L_WR2 |
0Cycles
(0 - 145Cycles)
|
tCCD_L_WR2 |
0Cycles
(0 - 145Cycles)
|
tCCD_L_WR2 |
0Cycles
(0 - 145Cycles)
|
tCCD_L_WR2 |
0Cycles
(0 - 145Cycles)
|
tCCD_L_WR2 |
0Cycles
(0 - 145Cycles)
|
tCCD_L_WR2 |
0Cycles
(0 - 145Cycles)
|
tCCD_L_WR2 |
0Cycles
(0 - 145Cycles)
|
tCCD_L_WR2 |
0Cycles
(0 - 145Cycles)
|
tCCD_L_WR2 |
0Cycles
(0 - 145Cycles)
|
tCCD_L_WR2 |
0Cycles
(0 - 145Cycles)
|
tCCD_L_WR2 |
0Cycles
(0 - 145Cycles)
|
tCCD_L_WR2 |
0Cycles
(0 - 145Cycles)
|
tCCD_L_WR2 |
0Cycles
(0 - 145Cycles)
|
tCCD_L_WR2 |
0Cycles
(0 - 145Cycles)
|
tCCD_L_WR2 |
0Cycles
(0 - 145Cycles)
|
tCCD_L_WTR |
0Cycles
(0 - 145Cycles)
|
tCCD_L_WTR |
0Cycles
(0 - 145Cycles)
|
tCCD_L_WTR |
0Cycles
(0 - 145Cycles)
|
tCCD_L_WTR |
0Cycles
(0 - 145Cycles)
|
tCCD_L_WTR |
0Cycles
(0 - 145Cycles)
|
tCCD_L_WTR |
0Cycles
(0 - 145Cycles)
|
tCCD_L_WTR |
0Cycles
(0 - 145Cycles)
|
tCCD_L_WTR |
0Cycles
(0 - 145Cycles)
|
tCCD_L_WTR |
0Cycles
(0 - 145Cycles)
|
tCCD_L_WTR |
0Cycles
(0 - 145Cycles)
|
tCCD_L_WTR |
0Cycles
(0 - 145Cycles)
|
tCCD_L_WTR |
0Cycles
(0 - 145Cycles)
|
tCCD_L_WTR |
0Cycles
(0 - 145Cycles)
|
tCCD_L_WTR |
0Cycles
(0 - 145Cycles)
|
tCCD_L_WTR |
0Cycles
(0 - 145Cycles)
|
tCCD_L_WTR |
0Cycles
(0 - 145Cycles)
|
tCCD_S_WTR |
0Cycles
(0 - 65Cycles)
|
tCCD_S_WTR |
0Cycles
(0 - 65Cycles)
|
tCCD_S_WTR |
0Cycles
(0 - 65Cycles)
|
tCCD_S_WTR |
0Cycles
(0 - 65Cycles)
|
tCCD_S_WTR |
0Cycles
(0 - 65Cycles)
|
tCCD_S_WTR |
0Cycles
(0 - 65Cycles)
|
tCCD_S_WTR |
0Cycles
(0 - 65Cycles)
|
tCCD_S_WTR |
0Cycles
(0 - 65Cycles)
|
tCCD_S_WTR |
0Cycles
(0 - 65Cycles)
|
tCCD_S_WTR |
0Cycles
(0 - 65Cycles)
|
tCCD_S_WTR |
0Cycles
(0 - 65Cycles)
|
tCCD_S_WTR |
0Cycles
(0 - 65Cycles)
|
tCCD_S_WTR |
0Cycles
(0 - 65Cycles)
|
tCCD_S_WTR |
0Cycles
(0 - 65Cycles)
|
tCCD_S_WTR |
0Cycles
(0 - 65Cycles)
|
tCCD_S_WTR |
0Cycles
(0 - 65Cycles)
|
tCL |
0Cycles
(0 - 72Cycles)
|
tCL |
0Cycles
(0 - 72Cycles)
|
tCL |
38Cycles
(4 - 72Cycles)
|
tCL |
0Cycles
(0 - 72Cycles)
|
tCL |
0Cycles
(0 - 72Cycles)
|
tCL |
40Cycles
(4 - 72Cycles)
|
tCL |
38Cycles
(4 - 72Cycles)
|
tCL |
38Cycles
(4 - 72Cycles)
|
tCL |
0Cycles
(0 - 72Cycles)
|
tCL |
40Cycles
(4 - 72Cycles)
|
tCL |
40Cycles
(4 - 72Cycles)
|
tCL |
0Cycles
(0 - 72Cycles)
|
tCL |
0Cycles
(0 - 72Cycles)
|
tCL |
40Cycles
(4 - 72Cycles)
|
tCL |
38Cycles
(4 - 72Cycles)
|
tCL |
0Cycles
(0 - 72Cycles)
|
tFAW |
0Cycles
(0 - 88Cycles)
|
tFAW |
0Cycles
(0 - 88Cycles)
|
tFAW |
0Cycles
(0 - 88Cycles)
|
tFAW |
0Cycles
(0 - 88Cycles)
|
tFAW |
0Cycles
(0 - 88Cycles)
|
tFAW |
0Cycles
(0 - 88Cycles)
|
tFAW |
0Cycles
(0 - 88Cycles)
|
tFAW |
0Cycles
(0 - 88Cycles)
|
tFAW |
0Cycles
(0 - 88Cycles)
|
tFAW |
0Cycles
(0 - 88Cycles)
|
tFAW |
0Cycles
(0 - 88Cycles)
|
tFAW |
0Cycles
(0 - 88Cycles)
|
tFAW |
0Cycles
(0 - 88Cycles)
|
tFAW |
0Cycles
(0 - 88Cycles)
|
tFAW |
0Cycles
(0 - 88Cycles)
|
tFAW |
0Cycles
(0 - 88Cycles)
|
tRAS |
0Cycles
(0 - 136Cycles)
|
tRAS |
0Cycles
(0 - 136Cycles)
|
tRAS |
80Cycles
(28 - 136Cycles)
|
tRAS |
0Cycles
(0 - 136Cycles)
|
tRAS |
0Cycles
(0 - 136Cycles)
|
tRAS |
70Cycles
(28 - 136Cycles)
|
tRAS |
0Cycles
(0 - 136Cycles)
|
tRAS |
70Cycles
(28 - 136Cycles)
|
tRAS |
0Cycles
(0 - 136Cycles)
|
tRAS |
70Cycles
(28 - 136Cycles)
|
tRAS |
0Cycles
(0 - 136Cycles)
|
tRAS |
80Cycles
(28 - 136Cycles)
|
tRAS |
70Cycles
(28 - 136Cycles)
|
tRAS |
0Cycles
(0 - 136Cycles)
|
tRAS |
80Cycles
(28 - 136Cycles)
|
tRAS |
80Cycles
(28 - 136Cycles)
|
tRC |
120Cycles
(1 - 500Cycles)
|
tRC |
0Cycles
(0 - 500Cycles)
|
tRC |
108Cycles
(1 - 500Cycles)
|
tRC |
120Cycles
(1 - 500Cycles)
|
tRC |
0Cycles
(0 - 500Cycles)
|
tRC |
0Cycles
(0 - 500Cycles)
|
tRC |
120Cycles
(1 - 500Cycles)
|
tRC |
0Cycles
(0 - 500Cycles)
|
tRC |
120Cycles
(1 - 500Cycles)
|
tRC |
0Cycles
(0 - 500Cycles)
|
tRC |
0Cycles
(0 - 500Cycles)
|
tRC |
0Cycles
(0 - 500Cycles)
|
tRC |
108Cycles
(1 - 500Cycles)
|
tRC |
108Cycles
(1 - 500Cycles)
|
tRC |
108Cycles
(1 - 500Cycles)
|
tRC |
0Cycles
(0 - 500Cycles)
|
tRCD |
38Cycles
(8 - 59Cycles)
|
tRCD |
40Cycles
(8 - 59Cycles)
|
tRCD |
40Cycles
(8 - 59Cycles)
|
tRCD |
40Cycles
(8 - 59Cycles)
|
tRCD |
0Cycles
(0 - 59Cycles)
|
tRCD |
0Cycles
(0 - 59Cycles)
|
tRCD |
0Cycles
(0 - 59Cycles)
|
tRCD |
0Cycles
(0 - 59Cycles)
|
tRCD |
0Cycles
(0 - 59Cycles)
|
tRCD |
0Cycles
(0 - 59Cycles)
|
tRCD |
38Cycles
(8 - 59Cycles)
|
tRCD |
38Cycles
(8 - 59Cycles)
|
tRCD |
0Cycles
(0 - 59Cycles)
|
tRCD |
0Cycles
(0 - 59Cycles)
|
tRCD |
40Cycles
(8 - 59Cycles)
|
tRCD |
38Cycles
(8 - 59Cycles)
|
tRFC1 |
0Cycles
(0 - 1200Cycles)
|
tRFC1 |
708Cycles
(1 - 1200Cycles)
|
tRFC1 |
0Cycles
(0 - 1200Cycles)
|
tRFC1 |
708Cycles
(1 - 1200Cycles)
|
tRFC1 |
766Cycles
(1 - 1200Cycles)
|
tRFC1 |
0Cycles
(0 - 1200Cycles)
|
tRFC1 |
708Cycles
(1 - 1200Cycles)
|
tRFC1 |
766Cycles
(1 - 1200Cycles)
|
tRFC1 |
0Cycles
(0 - 1200Cycles)
|
tRFC1 |
708Cycles
(1 - 1200Cycles)
|
tRFC1 |
0Cycles
(0 - 1200Cycles)
|
tRFC1 |
0Cycles
(0 - 1200Cycles)
|
tRFC1 |
0Cycles
(0 - 1200Cycles)
|
tRFC1 |
766Cycles
(1 - 1200Cycles)
|
tRFC1 |
0Cycles
(0 - 1200Cycles)
|
tRFC1 |
766Cycles
(1 - 1200Cycles)
|
tRFC2 |
416Cycles
(1 - 1200Cycles)
|
tRFC2 |
384Cycles
(1 - 1200Cycles)
|
tRFC2 |
416Cycles
(1 - 1200Cycles)
|
tRFC2 |
0Cycles
(0 - 1200Cycles)
|
tRFC2 |
0Cycles
(0 - 1200Cycles)
|
tRFC2 |
416Cycles
(1 - 1200Cycles)
|
tRFC2 |
0Cycles
(0 - 1200Cycles)
|
tRFC2 |
0Cycles
(0 - 1200Cycles)
|
tRFC2 |
0Cycles
(0 - 1200Cycles)
|
tRFC2 |
0Cycles
(0 - 1200Cycles)
|
tRFC2 |
416Cycles
(1 - 1200Cycles)
|
tRFC2 |
384Cycles
(1 - 1200Cycles)
|
tRFC2 |
0Cycles
(0 - 1200Cycles)
|
tRFC2 |
0Cycles
(0 - 1200Cycles)
|
tRFC2 |
384Cycles
(1 - 1200Cycles)
|
tRFC2 |
384Cycles
(1 - 1200Cycles)
|
tRFCsb |
0Cycles
(0 - 1200Cycles)
|
tRFCsb |
0Cycles
(0 - 1200Cycles)
|
tRFCsb |
0Cycles
(0 - 1200Cycles)
|
tRFCsb |
0Cycles
(0 - 1200Cycles)
|
tRFCsb |
338Cycles
(1 - 1200Cycles)
|
tRFCsb |
312Cycles
(1 - 1200Cycles)
|
tRFCsb |
0Cycles
(0 - 1200Cycles)
|
tRFCsb |
312Cycles
(1 - 1200Cycles)
|
tRFCsb |
0Cycles
(0 - 1200Cycles)
|
tRFCsb |
0Cycles
(0 - 1200Cycles)
|
tRFCsb |
312Cycles
(1 - 1200Cycles)
|
tRFCsb |
338Cycles
(1 - 1200Cycles)
|
tRFCsb |
312Cycles
(1 - 1200Cycles)
|
tRFCsb |
338Cycles
(1 - 1200Cycles)
|
tRFCsb |
0Cycles
(0 - 1200Cycles)
|
tRFCsb |
338Cycles
(1 - 1200Cycles)
|
tRP |
40Cycles
(8 - 60Cycles)
|
tRP |
0Cycles
(0 - 60Cycles)
|
tRP |
0Cycles
(0 - 60Cycles)
|
tRP |
0Cycles
(0 - 60Cycles)
|
tRP |
38Cycles
(8 - 60Cycles)
|
tRP |
0Cycles
(0 - 60Cycles)
|
tRP |
40Cycles
(8 - 60Cycles)
|
tRP |
0Cycles
(0 - 60Cycles)
|
tRP |
40Cycles
(8 - 60Cycles)
|
tRP |
0Cycles
(0 - 60Cycles)
|
tRP |
40Cycles
(8 - 60Cycles)
|
tRP |
0Cycles
(0 - 60Cycles)
|
tRP |
38Cycles
(8 - 60Cycles)
|
tRP |
0Cycles
(0 - 60Cycles)
|
tRP |
38Cycles
(8 - 60Cycles)
|
tRP |
38Cycles
(8 - 60Cycles)
|
tRRD_L |
0Cycles
(0 - 32Cycles)
|
tRRD_L |
0Cycles
(0 - 32Cycles)
|
tRRD_L |
0Cycles
(0 - 32Cycles)
|
tRRD_L |
0Cycles
(0 - 32Cycles)
|
tRRD_L |
0Cycles
(0 - 32Cycles)
|
tRRD_L |
0Cycles
(0 - 32Cycles)
|
tRRD_L |
0Cycles
(0 - 32Cycles)
|
tRRD_L |
0Cycles
(0 - 32Cycles)
|
tRRD_L |
0Cycles
(0 - 32Cycles)
|
tRRD_L |
0Cycles
(0 - 32Cycles)
|
tRRD_L |
0Cycles
(0 - 32Cycles)
|
tRRD_L |
0Cycles
(0 - 32Cycles)
|
tRRD_L |
0Cycles
(0 - 32Cycles)
|
tRRD_L |
0Cycles
(0 - 32Cycles)
|
tRRD_L |
0Cycles
(0 - 32Cycles)
|
tRRD_L |
0Cycles
(0 - 32Cycles)
|
tRTP |
0Cycles
(0 - 32Cycles)
|
tRTP |
0Cycles
(0 - 32Cycles)
|
tRTP |
0Cycles
(0 - 32Cycles)
|
tRTP |
0Cycles
(0 - 32Cycles)
|
tRTP |
0Cycles
(0 - 32Cycles)
|
tRTP |
0Cycles
(0 - 32Cycles)
|
tRTP |
0Cycles
(0 - 32Cycles)
|
tRTP |
0Cycles
(0 - 32Cycles)
|
tRTP |
0Cycles
(0 - 32Cycles)
|
tRTP |
0Cycles
(0 - 32Cycles)
|
tRTP |
0Cycles
(0 - 32Cycles)
|
tRTP |
0Cycles
(0 - 32Cycles)
|
tRTP |
0Cycles
(0 - 32Cycles)
|
tRTP |
0Cycles
(0 - 32Cycles)
|
tRTP |
0Cycles
(0 - 32Cycles)
|
tRTP |
0Cycles
(0 - 32Cycles)
|
tWR |
72Cycles
(5 - 240Cycles)
|
tWR |
0Cycles
(0 - 240Cycles)
|
tWR |
78Cycles
(5 - 240Cycles)
|
tWR |
0Cycles
(0 - 240Cycles)
|
tWR |
78Cycles
(5 - 240Cycles)
|
tWR |
72Cycles
(5 - 240Cycles)
|
tWR |
78Cycles
(5 - 240Cycles)
|
tWR |
0Cycles
(0 - 240Cycles)
|
tWR |
72Cycles
(5 - 240Cycles)
|
tWR |
0Cycles
(0 - 240Cycles)
|
tWR |
0Cycles
(0 - 240Cycles)
|
tWR |
72Cycles
(5 - 240Cycles)
|
tWR |
0Cycles
(0 - 240Cycles)
|
tWR |
0Cycles
(0 - 240Cycles)
|
tWR |
78Cycles
(5 - 240Cycles)
|
tWR |
0Cycles
(0 - 240Cycles)
|
Cache |
Efficient Cores Cache Voltage |
DefaultV
(Default - 2.000V)
|
Efficient Cores Cache Voltage Offset |
0mV
(-1 - 1mV)
|
Processor Cache Voltage |
DefaultV
(Default - 2.000V)
|
Processor Cache Voltage Offset |
0mV
(-1 - 1mV)
|
Efficient Cores Cache Voltage Mode |
Adaptive
|
Processor Cache Voltage Mode |
Adaptive
|