Each sub-competition consists of multiple stages. Check the stages for specific rules.
The point distribution of each stage is: 50-47-45-43-41-39-37-35-33-31-29-27-25-23-21-19-17-15-13-11-9-8-7-6-5-4-3-2-1 besides the SDR SDRAM memory stage which tops at 30pts
Art design by DaQuteness
| # | Participant | Stage 1 | Stage 2 | Stage 3 | Stage 4 | Stage 5 |
Points
|
| 1 |
60 pts
|
65 pts
|
65 pts
|
65 pts
|
56 pts
|
311 pts | |
| 2 |
53 pts
|
60 pts
|
60 pts
|
56 pts
|
65 pts
|
294 pts | |
| 3 |
56 pts
|
56 pts
|
56 pts
|
60 pts
|
60 pts
|
288 pts | |
| 4 |
65 pts
|
53 pts
|
50 pts
|
50 pts
|
43 pts
|
261 pts | |
| 5 |
45 pts
|
47 pts
|
47 pts
|
53 pts
|
53 pts
|
245 pts | |
| 6 |
37 pts
|
50 pts
|
53 pts
|
47 pts
|
47 pts
|
234 pts | |
| 7 |
41 pts
|
45 pts
|
37 pts
|
43 pts
|
45 pts
|
211 pts | |
| 8 |
39 pts
|
43 pts
|
43 pts
|
45 pts
|
41 pts
|
211 pts | |
| 9 |
33 pts
|
41 pts
|
45 pts
|
35 pts
|
154 pts | ||
| 10 |
43 pts
|
39 pts
|
31 pts
|
31 pts
|
144 pts |
Why 4P cpus? Just 4core enabled?
One core per module enabled
@Leeghoofd can you clarify? Can we just disable cores to meet the 4 core requirement?
Never
The "4P" option represents one core per compute unit mode - certainly available on gigabyte boards, supposedly a certain bios on CHV, not sure about asrock and msi. It was added because it's vaguely analagous to p-core modes on ADL (rankings like 12900K (8P)).
The difference compared to just disabling cores is that each core gets a full 3-wide decoder 100% of the time, a full 256-bit FPU 100% of the time, and an exlusive 2MB of L2 cache. You can look at ths as the "P-core" and the extra integer units that normally share these resources as the "E-core". Another way to think of it is disabling CMT.
I found a screenshot of the settings on a 990FX-UD7 but even cheapo gigabyte AM3+ boards like the 78LMT-USB3 have the setting. Also attached are block diagrams (By Shigeru23 - Made by uploader, CC BY 3.0, https://commons.wikimedia.org/w/index.php?curid=17130259) annotated to show the difference.
Realistically a 78LMT-USB3 even being a fairly bunnyextraction board but with true 1 core per cu mode will still beat a crosshair with disabled cores. Imagine 12900K with 4P and 4E-cores vs 8P...
I'm talking about the AM4 section but I guess that also applies.
Correct, no core disabling to simulate another CPU allowed
Log in or register to comment