|
Processor |
|
AVX2 Ratio Offset |
0.0x
(0.0 - 31.0x)
|
|
Core Voltage |
DefaultV
(Default - MultipleV)
|
|
Core Voltage Offset |
0.0000mV
(0.0000 - MultiplemV)
|
|
Processor Core IccMax |
511.750A
(1.000 - 4294967294.000A)
|
|
Reference Clock |
DefaultMHz
(Default - 200.000MHz)
|
|
Processor.Turbo.VoltageOverride |
|
Performance Core 0 Voltage Override |
DefaultV
(Default - 2.000V)
|
|
Performance Core 1 Voltage Override |
DefaultV
(Default - 2.000V)
|
|
Performance Core 2 Voltage Override |
DefaultV
(Default - 2.000V)
|
|
Performance Core 3 Voltage Override |
DefaultV
(Default - 2.000V)
|
|
Processor.Turbo.VoltageOffset |
|
Performance Core 0 Voltage Offset |
0.000mV
(0.000 - 0.999mV)
|
|
Performance Core 1 Voltage Offset |
0.000mV
(0.000 - 0.999mV)
|
|
Performance Core 2 Voltage Offset |
0.000mV
(0.000 - 0.999mV)
|
|
Performance Core 3 Voltage Offset |
0.000mV
(0.000 - 0.999mV)
|
|
Processor.Turbo.VoltageMode |
|
Performance Core 0 Voltage Mode |
Adaptive
|
|
Performance Core 1 Voltage Mode |
Adaptive
|
|
Performance Core 2 Voltage Mode |
Adaptive
|
|
Performance Core 3 Voltage Mode |
Adaptive
|
|
Processor.Turbo.Ratios |
|
1 Active Performance Core |
45x
(34 - 45x)
|
|
2 Active Performance Cores |
45x
(34 - 45x)
|
|
3 Active Performance Cores |
43x
(34 - 45x)
|
|
4 Active Performance Cores |
43x
(34 - 45x)
|
|
Processor.Turbo.RatioLimit |
|
Performance Core 0 |
45x
(34 - 45x)
|
|
Performance Core 1 |
45x
(34 - 45x)
|
|
Performance Core 2 |
45x
(34 - 45x)
|
|
Performance Core 3 |
45x
(34 - 45x)
|
|
Processor.Turbo |
|
Processor.PowerCurrent |
|
Turbo Boost Power Max |
4095.875W
(1.000 - 4095.875W)
|
|
Turbo Boost Power Time Window |
8Seconds
(1 - 128Seconds)
|
|
Turbo Boost Short Power Max |
4095.875W
(1.000 - 4095.875W)
|
|
Turbo Boost Short Power Max Enable |
Enable
|
|
Memory.XMP |
|
CommandRate |
0n
(0 - 3n)
|
|
CommandRate |
0n
(0 - 3n)
|
|
CommandRate |
0n
(0 - 3n)
|
|
CommandRate |
0n
(0 - 3n)
|
|
CommandRate |
0n
(0 - 3n)
|
|
CommandRate |
0n
(0 - 3n)
|
|
CommandRate |
0n
(0 - 3n)
|
|
CommandRate |
0n
(0 - 3n)
|
|
CommandRate |
0n
(0 - 3n)
|
|
CommandRate |
0n
(0 - 3n)
|
|
Frequency |
0MHz
(0 - 2403MHz)
|
|
Frequency |
3003MHz
(990 - 3003MHz)
|
|
Frequency |
0MHz
(0 - 2403MHz)
|
|
Frequency |
2801MHz
(990 - 2801MHz)
|
|
Frequency |
2403MHz
(990 - 2403MHz)
|
|
Frequency |
3003MHz
(990 - 3003MHz)
|
|
Frequency |
2403MHz
(990 - 2403MHz)
|
|
Frequency |
0MHz
(0 - 2403MHz)
|
|
Frequency |
2801MHz
(990 - 2801MHz)
|
|
Frequency |
0MHz
(0 - 2403MHz)
|
|
MCVoltage |
MultipleV
(0.50 - MultipleV)
|
|
MCVoltage |
0.00V
(0.00 - MultipleV)
|
|
MCVoltage |
MultipleV
(0.50 - MultipleV)
|
|
MCVoltage |
MultipleV
(0.50 - MultipleV)
|
|
MCVoltage |
MultipleV
(0.50 - MultipleV)
|
|
MCVoltage |
0.00V
(0.00 - MultipleV)
|
|
MCVoltage |
0.00V
(0.00 - MultipleV)
|
|
MCVoltage |
1.30V
(0.50 - MultipleV)
|
|
MCVoltage |
1.30V
(0.50 - MultipleV)
|
|
MCVoltage |
0.00V
(0.00 - MultipleV)
|
|
VDD |
1.25V
(0.80 - MultipleV)
|
|
VDD |
0.00V
(0.00 - MultipleV)
|
|
VDD |
1.35V
(0.80 - MultipleV)
|
|
VDD |
1.35V
(0.80 - MultipleV)
|
|
VDD |
0.00V
(0.00 - MultipleV)
|
|
VDD |
0.00V
(0.00 - MultipleV)
|
|
VDD |
0.00V
(0.00 - MultipleV)
|
|
VDD |
1.10V
(0.80 - MultipleV)
|
|
VDD |
1.10V
(0.80 - MultipleV)
|
|
VDD |
1.25V
(0.80 - MultipleV)
|
|
VDDQ |
1.10V
(0.80 - MultipleV)
|
|
VDDQ |
0.00V
(0.00 - MultipleV)
|
|
VDDQ |
0.00V
(0.00 - MultipleV)
|
|
VDDQ |
1.10V
(0.80 - MultipleV)
|
|
VDDQ |
1.25V
(0.80 - MultipleV)
|
|
VDDQ |
0.00V
(0.00 - MultipleV)
|
|
VDDQ |
0.00V
(0.00 - MultipleV)
|
|
VDDQ |
1.35V
(0.80 - MultipleV)
|
|
VDDQ |
1.35V
(0.80 - MultipleV)
|
|
VDDQ |
1.25V
(0.80 - MultipleV)
|
|
VPP |
1.80V
(1.50 - MultipleV)
|
|
VPP |
1.80V
(1.50 - MultipleV)
|
|
VPP |
1.80V
(1.50 - MultipleV)
|
|
VPP |
0.00V
(0.00 - MultipleV)
|
|
VPP |
1.80V
(1.50 - MultipleV)
|
|
VPP |
1.80V
(1.50 - MultipleV)
|
|
VPP |
0.00V
(0.00 - MultipleV)
|
|
VPP |
0.00V
(0.00 - MultipleV)
|
|
VPP |
1.80V
(1.50 - MultipleV)
|
|
VPP |
0.00V
(0.00 - MultipleV)
|
|
tCCD_L |
0Cycles
(0 - 54Cycles)
|
|
tCCD_L |
0Cycles
(0 - 54Cycles)
|
|
tCCD_L |
0Cycles
(0 - 54Cycles)
|
|
tCCD_L |
0Cycles
(0 - 54Cycles)
|
|
tCCD_L |
0Cycles
(0 - 54Cycles)
|
|
tCCD_L |
0Cycles
(0 - 54Cycles)
|
|
tCCD_L |
0Cycles
(0 - 54Cycles)
|
|
tCCD_L |
0Cycles
(0 - 54Cycles)
|
|
tCCD_L |
0Cycles
(0 - 54Cycles)
|
|
tCCD_L |
0Cycles
(0 - 54Cycles)
|
|
tCCD_L_WR |
0Cycles
(0 - 54Cycles)
|
|
tCCD_L_WR |
0Cycles
(0 - 54Cycles)
|
|
tCCD_L_WR |
0Cycles
(0 - 54Cycles)
|
|
tCCD_L_WR |
0Cycles
(0 - 54Cycles)
|
|
tCCD_L_WR |
0Cycles
(0 - 54Cycles)
|
|
tCCD_L_WR |
0Cycles
(0 - 54Cycles)
|
|
tCCD_L_WR |
0Cycles
(0 - 54Cycles)
|
|
tCCD_L_WR |
0Cycles
(0 - 54Cycles)
|
|
tCCD_L_WR |
0Cycles
(0 - 54Cycles)
|
|
tCCD_L_WR |
0Cycles
(0 - 54Cycles)
|
|
tCCD_L_WR2 |
0Cycles
(0 - 145Cycles)
|
|
tCCD_L_WR2 |
0Cycles
(0 - 145Cycles)
|
|
tCCD_L_WR2 |
0Cycles
(0 - 145Cycles)
|
|
tCCD_L_WR2 |
0Cycles
(0 - 145Cycles)
|
|
tCCD_L_WR2 |
0Cycles
(0 - 145Cycles)
|
|
tCCD_L_WR2 |
0Cycles
(0 - 145Cycles)
|
|
tCCD_L_WR2 |
0Cycles
(0 - 145Cycles)
|
|
tCCD_L_WR2 |
0Cycles
(0 - 145Cycles)
|
|
tCCD_L_WR2 |
0Cycles
(0 - 145Cycles)
|
|
tCCD_L_WR2 |
0Cycles
(0 - 145Cycles)
|
|
tCCD_L_WTR |
0Cycles
(0 - 145Cycles)
|
|
tCCD_L_WTR |
0Cycles
(0 - 145Cycles)
|
|
tCCD_L_WTR |
0Cycles
(0 - 145Cycles)
|
|
tCCD_L_WTR |
0Cycles
(0 - 145Cycles)
|
|
tCCD_L_WTR |
0Cycles
(0 - 145Cycles)
|
|
tCCD_L_WTR |
0Cycles
(0 - 145Cycles)
|
|
tCCD_L_WTR |
0Cycles
(0 - 145Cycles)
|
|
tCCD_L_WTR |
0Cycles
(0 - 145Cycles)
|
|
tCCD_L_WTR |
0Cycles
(0 - 145Cycles)
|
|
tCCD_L_WTR |
0Cycles
(0 - 145Cycles)
|
|
tCCD_S_WTR |
0Cycles
(0 - 65Cycles)
|
|
tCCD_S_WTR |
0Cycles
(0 - 65Cycles)
|
|
tCCD_S_WTR |
0Cycles
(0 - 65Cycles)
|
|
tCCD_S_WTR |
0Cycles
(0 - 65Cycles)
|
|
tCCD_S_WTR |
0Cycles
(0 - 65Cycles)
|
|
tCCD_S_WTR |
0Cycles
(0 - 65Cycles)
|
|
tCCD_S_WTR |
0Cycles
(0 - 65Cycles)
|
|
tCCD_S_WTR |
0Cycles
(0 - 65Cycles)
|
|
tCCD_S_WTR |
0Cycles
(0 - 65Cycles)
|
|
tCCD_S_WTR |
0Cycles
(0 - 65Cycles)
|
|
tCL |
0Cycles
(0 - 72Cycles)
|
|
tCL |
38Cycles
(4 - 72Cycles)
|
|
tCL |
0Cycles
(0 - 72Cycles)
|
|
tCL |
40Cycles
(4 - 72Cycles)
|
|
tCL |
32Cycles
(4 - 72Cycles)
|
|
tCL |
38Cycles
(4 - 72Cycles)
|
|
tCL |
32Cycles
(4 - 72Cycles)
|
|
tCL |
0Cycles
(0 - 72Cycles)
|
|
tCL |
0Cycles
(0 - 72Cycles)
|
|
tCL |
40Cycles
(4 - 72Cycles)
|
|
tFAW |
0Cycles
(0 - 88Cycles)
|
|
tFAW |
0Cycles
(0 - 88Cycles)
|
|
tFAW |
0Cycles
(0 - 88Cycles)
|
|
tFAW |
0Cycles
(0 - 88Cycles)
|
|
tFAW |
0Cycles
(0 - 88Cycles)
|
|
tFAW |
0Cycles
(0 - 88Cycles)
|
|
tFAW |
0Cycles
(0 - 88Cycles)
|
|
tFAW |
0Cycles
(0 - 88Cycles)
|
|
tFAW |
0Cycles
(0 - 88Cycles)
|
|
tFAW |
0Cycles
(0 - 88Cycles)
|
|
tRAS |
80Cycles
(28 - 136Cycles)
|
|
tRAS |
80Cycles
(28 - 136Cycles)
|
|
tRAS |
0Cycles
(0 - 136Cycles)
|
|
tRAS |
0Cycles
(0 - 136Cycles)
|
|
tRAS |
0Cycles
(0 - 136Cycles)
|
|
tRAS |
70Cycles
(28 - 136Cycles)
|
|
tRAS |
70Cycles
(28 - 136Cycles)
|
|
tRAS |
0Cycles
(0 - 136Cycles)
|
|
tRAS |
80Cycles
(28 - 136Cycles)
|
|
tRAS |
80Cycles
(28 - 136Cycles)
|
|
tRC |
0Cycles
(0 - 500Cycles)
|
|
tRC |
135Cycles
(1 - 500Cycles)
|
|
tRC |
116Cycles
(1 - 500Cycles)
|
|
tRC |
118Cycles
(1 - 500Cycles)
|
|
tRC |
118Cycles
(1 - 500Cycles)
|
|
tRC |
135Cycles
(1 - 500Cycles)
|
|
tRC |
0Cycles
(0 - 500Cycles)
|
|
tRC |
116Cycles
(1 - 500Cycles)
|
|
tRC |
0Cycles
(0 - 500Cycles)
|
|
tRC |
0Cycles
(0 - 500Cycles)
|
|
tRCD |
0Cycles
(0 - 59Cycles)
|
|
tRCD |
0Cycles
(0 - 59Cycles)
|
|
tRCD |
38Cycles
(8 - 59Cycles)
|
|
tRCD |
38Cycles
(8 - 59Cycles)
|
|
tRCD |
38Cycles
(8 - 59Cycles)
|
|
tRCD |
0Cycles
(0 - 59Cycles)
|
|
tRCD |
0Cycles
(0 - 59Cycles)
|
|
tRCD |
38Cycles
(8 - 59Cycles)
|
|
tRCD |
40Cycles
(8 - 59Cycles)
|
|
tRCD |
40Cycles
(8 - 59Cycles)
|
|
tRFC1 |
0Cycles
(0 - 1200Cycles)
|
|
tRFC1 |
884Cycles
(1 - 1200Cycles)
|
|
tRFC1 |
884Cycles
(1 - 1200Cycles)
|
|
tRFC1 |
708Cycles
(1 - 1200Cycles)
|
|
tRFC1 |
824Cycles
(1 - 1200Cycles)
|
|
tRFC1 |
708Cycles
(1 - 1200Cycles)
|
|
tRFC1 |
0Cycles
(0 - 1200Cycles)
|
|
tRFC1 |
0Cycles
(0 - 1200Cycles)
|
|
tRFC1 |
0Cycles
(0 - 1200Cycles)
|
|
tRFC1 |
824Cycles
(1 - 1200Cycles)
|
|
tRFC2 |
384Cycles
(1 - 1200Cycles)
|
|
tRFC2 |
480Cycles
(1 - 1200Cycles)
|
|
tRFC2 |
447Cycles
(1 - 1200Cycles)
|
|
tRFC2 |
480Cycles
(1 - 1200Cycles)
|
|
tRFC2 |
447Cycles
(1 - 1200Cycles)
|
|
tRFC2 |
0Cycles
(0 - 1200Cycles)
|
|
tRFC2 |
0Cycles
(0 - 1200Cycles)
|
|
tRFC2 |
0Cycles
(0 - 1200Cycles)
|
|
tRFC2 |
0Cycles
(0 - 1200Cycles)
|
|
tRFC2 |
384Cycles
(1 - 1200Cycles)
|
|
tRFCsb |
312Cycles
(1 - 1200Cycles)
|
|
tRFCsb |
364Cycles
(1 - 1200Cycles)
|
|
tRFCsb |
390Cycles
(1 - 1200Cycles)
|
|
tRFCsb |
312Cycles
(1 - 1200Cycles)
|
|
tRFCsb |
0Cycles
(0 - 1200Cycles)
|
|
tRFCsb |
390Cycles
(1 - 1200Cycles)
|
|
tRFCsb |
364Cycles
(1 - 1200Cycles)
|
|
tRFCsb |
0Cycles
(0 - 1200Cycles)
|
|
tRFCsb |
0Cycles
(0 - 1200Cycles)
|
|
tRFCsb |
0Cycles
(0 - 1200Cycles)
|
|
tRP |
38Cycles
(8 - 60Cycles)
|
|
tRP |
38Cycles
(8 - 60Cycles)
|
|
tRP |
0Cycles
(0 - 60Cycles)
|
|
tRP |
0Cycles
(0 - 60Cycles)
|
|
tRP |
0Cycles
(0 - 60Cycles)
|
|
tRP |
40Cycles
(8 - 60Cycles)
|
|
tRP |
40Cycles
(8 - 60Cycles)
|
|
tRP |
38Cycles
(8 - 60Cycles)
|
|
tRP |
38Cycles
(8 - 60Cycles)
|
|
tRP |
0Cycles
(0 - 60Cycles)
|
|
tRRD_L |
0Cycles
(0 - 32Cycles)
|
|
tRRD_L |
0Cycles
(0 - 32Cycles)
|
|
tRRD_L |
0Cycles
(0 - 32Cycles)
|
|
tRRD_L |
0Cycles
(0 - 32Cycles)
|
|
tRRD_L |
0Cycles
(0 - 32Cycles)
|
|
tRRD_L |
0Cycles
(0 - 32Cycles)
|
|
tRRD_L |
0Cycles
(0 - 32Cycles)
|
|
tRRD_L |
0Cycles
(0 - 32Cycles)
|
|
tRRD_L |
0Cycles
(0 - 32Cycles)
|
|
tRRD_L |
0Cycles
(0 - 32Cycles)
|
|
tRTP |
0Cycles
(0 - 32Cycles)
|
|
tRTP |
0Cycles
(0 - 32Cycles)
|
|
tRTP |
0Cycles
(0 - 32Cycles)
|
|
tRTP |
0Cycles
(0 - 32Cycles)
|
|
tRTP |
0Cycles
(0 - 32Cycles)
|
|
tRTP |
0Cycles
(0 - 32Cycles)
|
|
tRTP |
0Cycles
(0 - 32Cycles)
|
|
tRTP |
0Cycles
(0 - 32Cycles)
|
|
tRTP |
0Cycles
(0 - 32Cycles)
|
|
tRTP |
0Cycles
(0 - 32Cycles)
|
|
tWR |
0Cycles
(0 - 240Cycles)
|
|
tWR |
0Cycles
(0 - 240Cycles)
|
|
tWR |
72Cycles
(5 - 240Cycles)
|
|
tWR |
84Cycles
(5 - 240Cycles)
|
|
tWR |
0Cycles
(0 - 240Cycles)
|
|
tWR |
72Cycles
(5 - 240Cycles)
|
|
tWR |
84Cycles
(5 - 240Cycles)
|
|
tWR |
0Cycles
(0 - 240Cycles)
|
|
tWR |
90Cycles
(5 - 240Cycles)
|
|
tWR |
90Cycles
(5 - 240Cycles)
|
