Soft Machine's VISC Architecture Examined

While the pursuit of improved computing performance has historically involved pushing clock speeds, upping the core-count, increasing cache sizes and improving efficiency by any means possible, one company is striving to literally re-write the rules – or more accurately, the instruction set. Soft Machines recently announced licensing of their new ‘VISC’ architecture which involves a virtual instruction set that splits the workload of a single thread across multiple cores to radically improve overall instructions-per-clock performance.

New processor architectures and instruction sets are not always the easiest things to grasp but luckily for us Ian Cutress from Anandtech has been following the Soft Machine story for some time, and frankly the man is well up to speed. His recent article covering the emergence of the VISC architecture and Soft Machine's plans for the future makes for a very interesting read indeed. Here’s a sample:

“The main way of increasing performance, or in this case the instructions per unit frequency (instructions per clock, or IPC), is to expand the CPU architecture to allow more commands to be processed at once. Moving from a 3-wide out-of-order architecture to a 5-wide out-of-order architecture theoretically allows for a 66% increase in instruction throughput if (and only if) the code is sufficiently dense enough to extract those operations, and the other features in the architecture can ensure all the operations are fed every clock cycle.”

Read Ian's full and detailed article.


Please log in or register to comment.